It is known for a memory to be configured for double pumped operation in which the data rate (i.e. the rate at which data may be written to or read from the memory) is twice the clock frequency. Various advantages associated with this double pumping technique are known, not least of which is the doubled data transmission rate with respect to a single pumped configuration.
Adapting a memory to the double pumped is however not without its technical challenges, since not only must the memory be configured to operate at an internal clock frequency which is twice the external clock frequency it receives, various other different aspects of the configuration and operation of the memory can be affected.
The present techniques are concerned with addressing various technical challenges which arise in the context of configuring a memory device for double pumped operation.